Dynamic random access memory (DRAM) devices are the most commonly used type of semiconductor memory and, thus, are found in many integrated circuit designs. DRAM devices are also frequently embedded into application specific integrated circuits, such as processors and logic devices. A generic DRAM device includes a plurality of substantially identical semiconductor memory cell arrays, a plurality of bit lines, and a plurality of word lines that intersect the bit lines. Each memory cell array includes a plurality of memory cells arranged in rows and columns and each individual memory cell in the array is located at the intersection of a respective word line and a respective bit line.
Each individual memory cell includes a storage capacitor for storing data and an access device, such as a planar or vertical metal oxide semiconductor field-effect transistor (MOSFET), for allowing the transfer of data charges to and from the storage capacitor during reading and writing operations. Either the source or drain of the access device is connected to a corresponding bit line and the gate of the access device is connected to a corresponding word line. In certain DRAM device designs, memory cells are arranged in pairs to allow sharing of a bit line contact, which significantly reduces the overall memory cell size.
When the access device of one of the memory cells is activated by a signal on the word line, a data signal is transferred from the storage capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the storage capacitor of the memory cell. Because DRAM devices are a type of volatile memory that leaks stored charge, the data charge on the storage capacitor (corresponding to a “1” or “0”) is periodically refreshed during a refresh operation.
When data stored in one of the memory cells is read onto one of the bit lines, a potential difference is generated between the bit line of the respective memory cell and the bit line of another memory cell, which form a data line pair. A bit line sense amplifier connected to the bit line pair senses and amplifies the potential difference and transfers the data from the selected memory cells to a data line pair.
One goal of memory device designers is to pack more memory cells more densely into a smaller integrated circuit. Vertical memory cells feature an architecture in which the storage capacitor and access device are stacked vertically in a common trench. Vertical memory cells afford increased packing densities and other advantages in comparison to planar memory cells, in which size reduction was realized in the past primarily by reduction of the linear dimensions (i.e., the minimum lithographic feature size, F). For example, the packing density of vertical memory cells in a DRAM device is increased because the length of the vertical access device channel is decoupled from the minimum lithographic feature size. Consequently, vertical memory cells lack the scaling problems with, for example, reducing the gate-oxide thickness and increasing the channel doping concentration encountered when scaling planar access devices to smaller sizes. The vertical memory cell architecture also allows longer channel lengths without a proportional decrease in memory density, as is true in planar memory cells. Channel length may also be properly scaled in vertical memory cells relative to gate oxide thickness and relative to junction depth to reduce channel doping, minimize junction leakage, and increase data retention times.
Constructing DRAM devices using semiconductor-on-insulator (SOI) technology offers many advantages over counterpart devices built in bulk semiconductor substrates including, but not limited to, higher performance, absence of latch-up, higher packing density, and low voltage applications. In SOI technology, a thin semiconductor layer, often referred to as an SOI layer, is electrically isolated from a thicker semiconductor substrate by an insulating or dielectric material, e.g., a buried oxide or BOX layer. The access devices for the memory cells are built in a portion of the SOI layer termed the SOI body.
Floating body effects occur in vertical memory cells built using SOI technology. SOI technology eliminates junction capacitance problems observed in comparable bulk devices by electrically isolating the SOI body of transistor-type access devices from the underlying semiconductor material of the substrate. However, the SOI body may float at a potential that varies according to various conditions in which the transistor-type access device is operated.
Floating body effects are known to significantly degrade cell data retention time, which is most evident in long data retention time memory cells. Floating body effects originate from the accumulation of charge carriers in the channel region of the access device defined in the SOI body. A resultant leakage current is established via a parasitic bipolar transistor structure arising from the accumulated charge carriers. If uncompensated, the leakage current gradually discharges the storage capacitor. Floating body effects also cause fluctuations in the threshold voltage for the memory cell arising from the charge build up, which is extremely detrimental to conventional operation of transistor-type access devices.
What is needed, therefore, is a semiconductor structure for an SOI DRAM cell array with improved cell data retention times and methods of fabricating such semiconductor structures that overcome the disadvantages of conventional semiconductor structures and conventional methods of manufacturing such semiconductor structures.